1. Field of the Invention
The present invention relates to a method of forming an isolation film that isolates element regions by insulating film embedded in trenches (shallow trench isolation). The invention relates particularly to a method of forming the isolation film preferable for a semiconductor device having various kinds of transistors with gate insulating film of different thickness such as a flash memory.
2. Description of the Prior Art
With higher density of semiconductor devices, the shallow trench isolation that isolates the element regions by the insulating film embedded in the trenches has been used.
FIGS. 1A to 1F are sectional views showing a conventional manufacturing method of a semiconductor device in the order of process, in which the element regions are isolated by the shallow trench isolation.
First, as shown in FIG. 1A, the surface of a silicon substrate 11 is subjected to thermal oxidation to form a silicon oxide film (SiO2) 12. Then, a silicon nitride film (SiN) 13 is formed on the silicon oxide film 12 by a CVD (Chemical Vapor Deposition) method. Finally, a resist film 14 is formed on the silicon nitride film 13 by a photolithography method, in which a portion corresponding to an element isolation region is open.
Next, the silicon nitride film 13 is etched using the resist film 14 as a mask. Then, after having removed the resist film 14, the silicon oxide film 12 is etched using the silicon nitride film 13 as a mask, and the silicon substrate 11 is further etched to form a trench 15 as shown in FIG. 1B.
Next, as shown in FIG. 1C, the wall surface and the bottom surface of the trench 15 are subjected to thermal oxidation to form a silicon oxide film 16. Subsequently, SiO2 is deposited over the entire upper surface of the silicon substrate 11 to form a silicon oxide film 17 by a high-density plasma CVD method, and SiO2 is thus embedded in the trench 15.
Then, as shown in FIG. 1D, the silicon oxide film 17 is polished until the silicon nitride film 13 is exposed and the surface thereof is made to be flat by a CMP (Chemical Mechanical Polishing) method. Hereinafter, SiO2 embedded in the trench 15 is referred to as an isolation film (an element isolation film) 17a. 
Next, as shown in FIG. 1E, the silicon nitride film 13 is removed by wet etching using hot phosphoric acid. Subsequently, the silicon oxide film 12 is removed by wet etching using hydrofluoric acid (HF). Then, a sacrifice oxide film 18 is formed on the surface of the silicon substrate 11 by a thermal oxidation method. Ion implantation of conductive impurities for threshold adjustment, for example, is performed onto the surface of the silicon substrate 11 via the sacrifice oxide film 18.
Next, after having removed the sacrifice oxide film 18, a gate oxide film 19 is formed on the surface of the silicon substrate 11 as shown in FIG. 1F. Subsequently, a gate electrode is formed in a predetermined pattern on the gate oxide film 19, the conductive impurities are implanted onto the silicon substrate 11 using the gate electrode as a mask, and a source/drain region is formed. With this procedure, the semiconductor device in which the element regions are isolated by the shallow trench isolation (isolation film 17a) is manufactured.
However, the above-described conventional manufacturing method of the semiconductor device has the following problems. Specifically, when removing the silicon oxide film 12 and the sacrifice oxide film 18 by hydrofluoric acid, recess called a divot can occur in the isolation film 17a because the isolation film 17a is also etched, as shown in FIG. 2.
When forming the flash memory or the like, the gate electrode is formed on the isolation film 17a as well. However, if a part of the gate electrode is embedded in the divot area, electric field concentrates on this area to generate a parasitic transistor having a low threshold voltage. A hump occurs in the voltage-current characteristic of a transistor due to the parasitic transistor, as shown in FIG. 3. This changes the threshold voltage of the transistor to cause a problem such as an increase of an off-leak current.
To prevent the divot from occurring even if the isolation film 17a is etched by hydrofluoric acid, isotropic etching may be performed to the silicon nitride film 13 before forming the isolating film 17a. Alternatively, as shown in FIG. 4, the trench 15 may be formed after forming sidewalls 19 on the sides of the silicon nitride film 13 (Patent Application Publication (KOKAI) Hei11-260906, 2000-208613).
However, such processes are inadequate as countermeasures to the divot in manufacturing the flash memory.
FIG. 5 is a schematic view showing the constitution of the flash memory. The flash memory has a memory cell section where a transistor having two gate electrodes (a floating gate 21a and a control gate 21b) is formed, a low-voltage operation section where a transistor driven by a low-voltage of approximately 1.2V to 3.3V is formed, and a high-voltage operation section where a transistor driven by a high-voltage of approximately 20V is formed. The thickness of gate insulating film 23 in the low-voltage operation section is thinner than that of a gate insulating film 24 of the high-voltage operation section. Note that the thickness of a gate insulating film 22 in the memory cell section is the same as that of the gate insulating film 23 of the low-voltage operation section.
The gate insulating films of these transistors are generally formed simultaneously. In other words, after having formed a thick insulating film, the resist film is formed on the insulating film in the high-voltage operation section, and the insulating film in the low-voltage operation section and the memory cell section (hereinafter, simply referred to as a ‘low-voltage operation section’) is etched only by 100 angstroms to make it thin.
In the case of preventing occurrence of the divots by the isotropic etching to the silicon nitride film, when the isotropic etching is performed to the silicon nitride film according to the etching condition that the divots do not occur in the high-voltage operation section, the divots occur in the low-voltage operation section although the divots do not occur in the high-voltage operation section, as shown in FIG. 6. When the isotropic etching is performed to the silicon nitride film according to the etching condition that the divots do not occur in the low-voltage operation section, the isolation film remains on the element region of the high-voltage operation section, which makes the element region narrow and hampers high integration.
Similarly, in the case of preventing occurrence of the divots by the sidewalls, formation of the sidewalls according to the formation condition that the divots do not occur in the high-voltage operation section does not exert effect to prevent the divots in the low-voltage operation section, and formation of the sidewalls according to the formation condition that the divots do not occur in the low-voltage operation section leaves the isolation film on the element region in the high-voltage operation section.
Note that Patent Application Publication (KOKAI) 2001-94075 describes a method to prevent occurrence of the divots at the edge portion of the isolation film (shallow trench isolation). However, a problem similar to the above-described one occurs in the case that a peripheral circuit section is provided with two kinds of transistors with gate insulating film of different thickness.